The present invention relates to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a three-dimensional (3D) nonvolatile memory device and a method for fabricating the same.
Nonvolatile memory devices retain stored data even when power is interrupted. Two-dimensional (2D) memory devices fabricated in a single layer on a silicon substrate have limitations in improving integration density. Therefore, 3D nonvolatile memory devices with memory cells stacked vertically from a silicon substrate have been proposed.
Hereinafter, a conventional method for fabricating a 3D nonvolatile memory device will be described with reference to the accompanying drawings.
FIGS. 1A to 4B illustrate a conventional process for fabricating a 3D nonvolatile memory device. Herein, Figures “A” are cross-sectional views of intermediate resulting structures, and Figures “B” are plan views at a height A-A′ of Figures “A”.
Referring to FIGS. 1A and 1B, an interlayer insulating layer 11 and a gate electrode conductive layer 12 are formed on a substrate 10. The gate electrode conductive layer 12 and the interlayer insulating layer 11 are etched to form contact holes H exposing the substrate 10.
A gate dielectric layer 1 is formed on inner walls of the contact holes H. The contact holes H having the gate dielectric layer 1 formed on their inner walls are filled with a channel layer 2, thereby forming a lower select transistor LOWER TR of a vertical string.
A plurality of interlayer insulating layers 11 and a plurality of gate electrode conductive layers 12 are alternately formed on the substrate 10 having the lower select transistor LOWER TR formed thereon.
The interlayer insulating layers 11 and the gate electrode conductive layers 12 are selectively etched to form a plurality of contact holes H exposing the substrate 10.
Referring to FIGS. 2A and 2B, a charge blocking layer 13 is formed on inner walls of the contact holes H. Herein, the charge blocking layer 13 prevents charges from passing through a charge trapping layer 14 and moving toward the gate electrodes.
A charge trapping layer 14 is formed on the charge blocking layer 13. Herein, the charge trapping layer 14 traps charges in a deep-level trapping site and serves as a substantial data storage. Generally, the charge trapping layer 14 is formed of nitride.
The contact holes H having the charge blocking layer 13 and the charge trapping layer 14 formed on their inner walls are filled with a tunnel insulating layer 15. Herein, the tunnel insulating layer 15 serves as an energy barrier layer because of tunneling of charges.
Referring to FIGS. 3A and 3B, a center region of the tunnel insulating layer 15 is etched to form channel trenches. The channel trenches are filled with a channel layer to form a plurality of channels 16 protruding from the substrate 10.
An upper select transistor UPPER TR is formed on the resulting structure including the channels 16. Herein, the upper select transistor UPPER TR is formed in the same way as the lower select transistor LOWER TR. Thus, a detailed description of a process for forming the upper select transistor UPPER TR will be omitted for conciseness.
Referring to FIGS. 4A and 4B, a plurality of mask patterns (not shown) are formed on the resulting structure including the upper select transistor UPPER TR. Herein, the mask patterns cover a memory cell (MC) region and extend in a first direction I-I′. Using the mask patterns as an etch barrier, the interlayer insulating layer 11 and the gate electrode conductive layer 12 are etched to form a plurality of gate electrodes 12A. The etched region is filled with an insulating layer 17.
In this way, a plurality of memory cells MC each including the tunnel insulating layer 15, the charge trapping layer 14, the charge blocking layer 13, and the gate electrode 12A surrounding the outer surface of the vertical channel 16 are formed.
Herein, the memory cells MC stacked along the same channel 16 are connected in series between the lower select transistor LOWER TR and the upper select transistor UPPER TR to constitute a string ST. That is, the conventional 3D nonvolatile memory device has a plurality of strings ST arranged vertically from the substrate 10.
Also, the memory cells MC connected to the gate electrode 12A (i.e., the memory cells arranged in the first direction) operate as one page.
According to the conventional art described above, because the plurality of gate electrode conductive layers are stacked in forming memory cells MC, it is possible to provide a 3D nonvolatile memory device with a string structure arranged vertically from a substrate.
However, according to the above structure, the gate electrode conductive layers of the respective layers face each other over wide surface area, and the material of the conductive layers is limited to polysilicon due to process limits. Thus, word-line resistance/capacitance values are large, and the resulting RC delay degrades the performance of the memory device.
Furthermore, according to the conventional art described above, the channels 16 are formed after forming the gate electrode conductive layers 12, the charge blocking layer 13, the charge trapping layer 14, and the tunnel insulating layer 15. That is, because the fabrication process of the 3D nonvolatile memory device is performed in reverse order of that of the planar nonvolatile memory device, the characteristics of the memory device are degraded, as will be described below in more detail.
First, the layer quality of the tunnel insulating layer 15 is degraded because the tunnel insulating layer 15 is formed at the last stage and the channel trenches are formed by etching the center region of the tunnel insulating layer 15.
Second, a high-temperature monocrystalline layer is difficult to grow because the charge blocking layer 13, the charge trapping layer 14, and the tunnel insulating layer 15 may be damaged during the process of forming the channel layer within the channel trenches and thus the channels 16 of monocrystalline silicon may fail to be formed. Therefore, the current flow in the channels 16 is lowered and the uniformity of threshold voltage distribution is degraded.
Meanwhile, the conventional 2D memory device has one drain select line per memory block. However, the 3D memory device has a plurality of memory cells stacked vertically from a substrate. Therefore, if the 3D memory device has one drain select line per memory block like the conventional memory device, it has a limitation in performing read/write operations by controlling the plurality of memory cells.